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We are pleased to announce the release of NxSDK 0.8.0. The installation files are located at /nfs/ncl/releases. Installation instructions stay the same as of 0.7 release. Getting Started guides are available for download here.

The release is available for all participants who have signed the INRC participation agreement and have access to the INRC Cloud.

New Features/Improvements

NxNet

  • Spike Receivers are enabled in NxNet for asynchronous and interactive probing of spikes

  • Enhancements were added to performance framework to report phase wise distribution including energy metrics and new workloads and categories have been added

  • Logging support is now enabled within NxSDK

  • Compiler optimizations to shorten compilation time

  • Addition of the neuron API to simplify the construction of multi-compartment neurons. See Neuron and NeuronPrototype documentation for details

  • Energy probes are now enabled on all platforms (WM, Nahuku) except KapohoBay (USB)

  • Improved stability and speedup of NxSDK on KapohoBay (USB)

Jupyter Tutorials

Feature Covered

Description

Category

i_performance_pro filing.ipynb

Performance Profiling (Execution Time and Energy)

This tutorial demonstrates how to measure the performance of your networks from the perspective of time, energy and power utilization as well as phase-wise distribution

Probes

j_soft_reset_net .ipynb

neuron API

This tutorial demonstrates soft reset membrane voltage at NxNet level using neuron API

NxNet

k_interactive_spi ke_sender_receive r.ipynb

Interactive SpikeGen and Spike Receiver

This tutorial demonstrates how to set up spike generators (basic and interactive) which enable to send stimuli both before and during the run. It also highlights the use of Spike Receivers to receive spikes in a non-blocking manner during the run

Spike Injection, Probes

l_snip_for_compa rtment_setup_with _NxNet_C.ipynb

NxNet C API

This tutorial demonstrates how to use NxNet C API to setup compartments

SNIP

m_independent_net works_in_same_ru n.ipynb

networks

This tutorial demonstrates that several independent and disconnected networks can be configured in the same run

NxNet

NxCore

  • Snips can now run on any lakemont on any chip provided, number of chips allocated > chipId for the snip.

  • Added Tutorial 21 demonstrating the multi-lmt snips api.

Major bug fixes for release

  • Deadlock arising from incorrect packing of synapses when learning is enabled has been fixed. This fix was a regression in 0.7.5 where a fix was put in to syn pack/unpack mechanism.

  • Memory leaks in probes has been fixed on host

  • Fixed a problem where, depending on the compartment ordering, compartment voltage may have non-zero decay even though voltage decay is set to 0.

  • Issue with using the spike generator to send spikes selectively across multiple net.run invocations has been fixed.

Known Issues

  • In certain circumstances, compressionMode = DENSE can cause undefined behavior. We recommend not specifying dense mode unless you truly need it.

  • Due to limited memory availability on the embedded device (Lakemont), allocating large memory segments within SNIPs might result in a linking error such as

    collect2: error: ld returned 1 exit status
/usr/bin/ld: temp/launcher.link section `.data' will not fit in region `DTCM'
/usr/bin/ld: region `DTCM' overflowed by 472005 bytes

    Reduce the memory utilization or use efficient packing protocols to create your data structures. If you are getting these errors while using execution time/energy probes, use binning with appropriate bin size.

API Changes/Deprecations

  • NxSDK module layout has been refactored to support new generations of hardware. Common code was moved to the base level of the module. Some user code might need to modify their imports if they are using these sub-modules (nxsdk.arch.n2a.compiler -> nxsdk.compiler, nxsdk.arch.n2a.graph -> nxsdk.graph and so on).

  • Removed chipGen parameter from NxCore board.run interface. Chip generation is now automatically configured.

  • avoid-deadlock is removed from list of valid compiler options.

  • Learning rule specification using bracket expressions, i.e. (v+C), requires expanding out the terms for certain ranges of C values. See Specifying a Learning Rule documentation for details.

  • ChipId is now a 3D structure with x,y,z fields, while the id union remains 14 bits. This will better support the topology of the upcoming Poihiki Springs systems.

  • Various nx_sw_* and nx_ne_* functions are renamed to nx_min_* and nx_max_* for improved clarity with the 3D coordinates.

  • The nx_phys_chipid/nx_phys_coreid functions are deprecated, replaced by nx_nth_chipid/nx_nth_coreid. The new functions return ChipId or CoreId's id fields that increase monotonically with n. That is, the order in which chips are connected on the FPIO serial chain is now hidden. Therefore nx_nth_chipid(0) will always be nx_min_chipid() and nx_nth_chipid(nx_num_chips()-1) will always be nx_max_chipid() Requesting an out-of-bounds core or chip will exit with an error.

  • runState structure's fields, time and nsteps have been renamed to time_step and total_steps respectively.

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