Tuesday, October 31, 2023, @ 8:00-9:00am PT you are invited to attend an INRC Forum talk from Udayan Ganguly of IIT Bombay.

Title:
Combinatorial Optimization using Neuromorphic Oscillators: Implementing n-city TSP Solution to n-oscillators compared to n^2 oscillators.

Abstract:
Neural Networks have long been a mainstream technique to solve optimization problems. A classic example is the Travelling Salesman Problem (TSP) which is NP-hard. Using a Hopfield-Tank representation, an n-city problem is mapped to a cost function of n 2 interacting neural units. Stochastic gradient descent helps achieve the global minima. Due to the nature of the TSP problem, the cost function has to penalize invalid sub-routes (non-Hamiltonian cycles) and minimize the travel cost simultaneously. In addition, there is a starting point and travel direction associated with `2n' degeneracy. Previously, a cellular neuronal approach was proposed where the neural units were replaced with oscillators. The phase relations determined the output solution. Multiphase clusters of these oscillators solved the degeneracy issue.
We propose an n-oscillator cost function for an n -city TSP. Since a group of single frequency oscillator phases are naturally ordered and circular in a system, the proposed method exploits the true potential of oscillator nodes. The sub-routes and degeneracy are eliminated by design in addition to massively increasing the scaling potential (n vs. n^2 ). It was also found that the proposed n- mapping can converge to the optimum tour much faster (about 100 times for a 5-city problem) than for n^2 mapping. Our approach projects hardware efficiency in terms of area footprint, computation time and energy. With coupled single device-based compact nanoscale oscillator systems becoming increasingly viable in hardware, efficient cost function mappings of hard problems using oscillator phases, as shown here, is critical to solving large graphical optimization problems.

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Open

Udayan Ganguly

Bio: Udayan Ganguly received the B.Tech. degree in Metallurgical Engineering from the IIT Madras, in 2000 and the M.S. and Ph.D. degrees in Materials Science and Engineering at Cornell University, Ithaca, NY, in 2005 and 2006 respectively. In 2006, Udayan joined Applied Materials to serve as the technical lead for Flash Memory Applications Development at Applied Materials’ Front End Product Division, Sunnyvale, CA. He joined Dept. of Electrical Engineering in 2010. He has authored/ co-authored 50+ journal articles, 90+ conference articles, and 25+ patents (applied/granted). His research interests are in semiconductor device physics and processing technologies for advanced memory, computing, and neuromorphic systems. He works to augment national semiconductor manufacturing capability at Semi-Conductor Labs, Chandigarh, for which he has won the Dr. PK Patwardhan Technology Development Award 2018. He has enabled the first-ever indigenous memory technology adoption at SCL at 180nm in 2021. He has led the Detailed Project Report for India Semiconductor R&D Center commissioned by O/o PSA which has informed the National Semiconductor Policy 2021 for the semiconductor manufacturing ecosystem. He has won the Kalam Technology Innovation National Fellowship 2022. He has been an Editor for IEEE Electron Devices Letters since 2020. He currently serves as the first Professor in Charge for IITB Center for Semiconductor Technologies (SemiX).

Recording:

For the recording and slides, see the full INRC Forum 2023 Schedule (accessible only to INRC Affiliates and Engaged Members).

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